The Expert of IP Core & Embedded

UDP100G/40G/25G/10G/1G IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time.
DesignGateway provide free evaluation demo file for Intel® FPGA boards. You can evaluate UDP10G-IP core on real board before purchasing.

• All Hard wired Logic TCP Offloading Engine TOE-IP core series
• Super Low Latency UDP(Rx/Tx)-IP for Fintech Visit here
  
  

Features

• All hardware logic to achieve CPU-less system
• Support IPv4 protocol
• Support one port connection
• Transmit/Receive buffer size, programmable on HDL for optimized resource
• Simple data interface by standard FIFO interface
• Simple control interface by standard register interface
• Multicast/broadcast Tx feature customization
• Super low-latency DG 10G EMAC-IP for UDP10G-IP core (Option) Learn more
• Provide free evaluation sof file for FPGA Development Kits (1 hour time limited)
• Reference design is included in IP core product

Block diagram

UDP100G-IP
UDP40G-IP * Click to show more detail	UDP25G-IP * Click to show more detail	UDP10G-IP * Click to show more detail	UDP1G-IP * Click to show more detail

Videos on YouTube

UDP-IP Introduction

Reference Design Introduction

UDP-IP Performance Demo

UDP-IP Application Examples

Document & Demo sof file download

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Document name	UDP100G/40G/25G/10G/1G-IP
UDP-IP core Presentation	Rev2.0AE
DG EMAC-IP Presentation (for UDP10G-IP)	Rev1.0AE
IP core simple introduction Blog	High efficiency up to 4963MB/sec UDP-IP transfer Evaluation Demo UDP-IP ideal for applications that require real-time & multicast

Support Devices	Arria® 10 GX/SX, Cyclone 10 GX, Arria V GX, Cyclone V E
IP core & Option	Datasheet	Reference Design Document	Demo Instruction	FPGA Setup Document	Free Evaluation file Get Password
UDP100G-IP	Rev1.0	Rev1.0	Rev1.1	Rev2.0	Agilex F-Series
UDP40G-IP	Rev1.1	Rev1.0	Rev1.0	-	Arria® 10 GX
UDP25G-IP	Rev1.0	Rev1.0	Rev1.0	Rev2.0	Agilex F-Series
UDP10G-IP	Rev1.2	Rev1.3	Rev1.3	Rev3.2	Arria® 10 SX Arria® 10 GX
10G25G EMAC-IP	Rev1.0	Rev1.0	Rev1.0		Cyclone® 10 GX
UDP1G-IP	Rev1.5	Rev1.2	Rev2.0	Rev2.0	Arria 10 GX Arria 10 SX Arria V GX Cyclone V E

Super low-latency DG 10GbE MAC core for UDP10G-IP

DG 10GbE MAC core implements the MAC layer for UDP10G-IP core and fully compatible with Intel MAC. It has many advantages. Super low-latency, Tx=19.2nsec, Rx=44.8nsec. Minimized resource usage, ? of Intel MAC core. Very low price, 1/5 of Intel MAC core.

	DG 10GEMAC-IP	Intel 10GEMAC
Tx latency (clk freq.=156.25MHz)	19.2ns (3clk)	76.8ns (12clk)
Rx latency (clk freq.=156.25MHz)	44.8ns (7clk)	83.2ns (13clk)
ALMs	1362	1617
Registers	1259	3015
Block Memory	0	2320

Free sof file for evaluation

DesignGateway provide 1-hour limitation free sof file for Intel® FPGA Development Boards. You can evaluate UDP100G/40G/25G/10G/1G-IP core on real board before purchasing.