The Expert of IP Core & Embedded

UDP1G IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate UDP1G-IP core on real board before purchasing.

• All Hard wired Logic TCP Offloading Engine "TOE10G-IP" and "TOE1G-IP"

Features

• All hardware logic to achive CPU-less system
• Support IPv4 protocol
• Support one port connection
• Transmit/Receive buffer size, programmable on HDL for optimized resource
• Simple data interface by standard FIFO interface
• Simple control interface by standard register interface
• One clock domain interface by fixed 125 MHz clock frequency
• Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
• Rerference design is included in IP core product

Block diagram

Document & Demo bit file download

Common Documents

Document name	Revision
UDP1G-IP core Presentation	Rev1.01E

Document Name	7-Series
UDP1G-IP core Datasheet	Rev1.1
Reference Design Document	Rev1.1
Demo Instruction Document	Rev1.1
Evaluation bit file & Apps for PC Get Password	ZC706/KC705/AC701
Demo Video

Free bit file for evaluation

DesignGateway provide 1-hour limitation bit file for Xilinx FPGA Development Boards. You can evaluate UDP1G-IP core on real board before purchasing.