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The Expert of IP Core & Embedded


UDP-IP core seriesUDP/IP stack implementation by all hardware logic

FeaturesBlock diagramDocument DownloadApplications
UDP10G-IP

UDP100G/40G/25G/10G/1G IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide free demo file for Xilinx FPGA boards. You can evaluate UDP10G-IP core on real board before purchasing.

Features

  • All hardware logic to achieve CPU-less system
  • Support IPv4 protocol
  • Support one port connection
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • Multicast/broadcast Tx feature customization
  • 19.2ns Super low-latency DG 10G25G EMAC-IP for UDP25G/10G-IP core (Option) Learn more
  • Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
  • Reference design is included in IP core product

Block diagram


UDP100G-IP

UDP40G-IP
* Click to show more detail

UDP25G-IP
* Click to show more detail

UDP10G-IP
* Click to show more detail

UDP1G-IP
* Click to show more detail


Videos on YouTube


UDP-IP Introduction

Reference Design Introduction

10G25G EMAC-IP Introduction

UDP-IP Performance Demo

UDP-IP Application Examples


25GEMAC/PCS +RS-FEC-IP
1. Introduction

25GEMAC/PCS +RS-FEC-IP
2. Comparison with EMAC

25GEMAC/PCS +RS-FEC-IP
3. Demo

Document & Demo bit file download

Please receive technical document update from DG News Letter. Subscribe to DG News
Technical document update page
Document name UDP100G/40G/25G/10G/1G-IP
UDP-IP core Presentation Rev2.0XE
DG 10G25G EMAC-IP Presentation Rev1.0XE
IP core simple introduction Blog High efficiency up to 4963MB/sec UDP-IP transfer Evaluation Demo
UDP-IP ideal for applications that require real-time & multicast

Support Devices Alveo, Zynq UltraScale+, Kintex UltraScale+,, Kintex UltraScale
Zynq-7000, Kintex-7, Artix-7
IP core &
Option
Datasheet Reference Design Document Demo Instruction FPGA Setup Document Free Evaluation file Get Password
UDP100G-IP Rev1.1 Rev1.0 Rev1.1 Rev3.3 U250
KCU116
KU15P
UDP40G-IP Rev1.1 Rev1.0 Rev1.0 - ZCU102
ZCU106
KCU105
UDP25G-IP Rev1.1 Rev1.1 Rev1.0 Rev2.5 ZCU111
KCU116
KU15P
25GEMAC/PCS +RS-FEC-IP Rev1.0 Rev1.0 Rev1.0 KCU116
UDP10G-IP Rev1.5 Rev1.4 Rev2.1 Rev3.3 ZCU111
ZCU102
KCU116
KCU105
10G25G EMAC-IP Rev1.3
UDP1G-IP Rev1.2 Rev1.1 Rev2.0 Rev3.0 ZC706
KC705
AC701

Min. 19.2ns Super low-latency DG 10G25G EMAC IP core

DG 10G25GEMAC core implements the MAC layer for UDP10G-IP core and highly compatible with Xilinx MAC. It has many advantages.

  • Super low-latency, Tx=19.2nsec, Rx=44.8nsec.
  • Minimized resource usage.
  • Very low price, 1/5 of Xilinx MAC core.

DG 10G25GEMAC-IP Xilinx 10GEMAC
Tx latency (clk freq.=156.25MHz) 19.2ns (3clk) 19.2ns (3clk)
Rx latency (clk freq.=156.25MHz) 44.8ns (7clk) 115.2ns (18clk)
CLB LUTs 1873 3498
CLB Registers 1072 3291
CLB 326 694

Free bit file for evaluation

DesignGateway provide 1-hour limitation bit file for Xilinx FPGA Development Boards. You can evaluate UDP100G/40G/25G/10G/1G-IP core on real board before purchasing.

Suitable Applications


Radar system

Marine sonar

Network game Console

Delay Tolerant Network
(DTN) Investigation


Alliance Partner


Design Gateway Co., Ltd.

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