UDP/IP Stack Offloading Engine IP Core for FPGA

UDP-IP core seriesUDP/IP stack implementation by all hardware logic

Features┃Block diagram┃Document Download┃Applications

UDP100G/40G/25G/10G/1G IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for AMD FPGA. It helps you to reduce development time.
DesignGateway provide free demo file for AMD FPGA boards. You can evaluate UDP10G-IP core on real board before purchasing.

All Hard wired Logic TCP Offloading Engine "TOE-IP core series"
Super Low Latency UDP(Rx/Tx)-IP for Fintech Visit here

Features

All hardware logic to achieve CPU-less system
Support IPv4 protocol
Support one port connection
Transmit/Receive buffer size, programmable on HDL for optimized resource
Simple data interface by standard FIFO interface
Simple control interface by standard register interface

Multicast/broadcast Tx feature customization
19.2ns Super low-latency DG 10G25G EMAC-IP for UDP25G/10G-IP core (Option) Learn more
Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
Reference design is included in IP core product
UDP-IP for AMD FPGAs listed on AMD Adaptive Computing Partner Solutions

Block diagram

Videos on YouTube

UDP-IP Introduction	Reference Design Introduction	10G25G EMAC-IP Introduction	UDP-IP Performance Demo	UDP-IP Application Examples

25GEMAC/PCS +RS-FEC-IP 1. Introduction	25GEMAC/PCS +RS-FEC-IP 2. Comparison with EMAC	25GEMAC/PCS +RS-FEC-IP 3. Demo on AMD KCU116

Document & Demo bit file download

Technical document update page

Document name	UDP100G/40G/25G/10G/1G-IP
UDP-IP core Presentation	Rev2.0XE
DG 10G25G EMAC-IP Presentation	Rev1.0XE
IP core simple introduction Blog	High efficiency up to 4963MB/sec UDP-IP transfer Evaluation Demo UDP-IP ideal for applications that require real-time & multicast

Support Devices	Versal AI Core, Alveo, Zynq UltraScale+, Kintex UltraScale+,, Kintex UltraScale Zynq-7000, Kintex-7, Artix-7
IP core & Option	Datasheet	Reference Design Document	Demo Instruction	FPGA Setup Document	Free Evaluation file
UDP100G-IP					VCK190 U250 KCU116 KU15P
UDP40G-IP					ZCU102 ZCU106 KCU105
UDP25G-IP					VCK190 ZCU111 KCU116 KU15P
25GEMAC/PCS +RS-FEC-IP					KCU116
UDP10G-IP					VEK280 ZCU111 ZCU102 KCU116 KCU105
10G25G EMAC-IP
UDP1G-IP					ZC706 \| KC705 \| AC701

Min. 19.2ns Super low-latency DG 10G25G EMAC IP core

DG 10G25GEMAC core implements the MAC layer for UDP10G-IP core and highly compatible with AMD MAC. It has many advantages.

Super low-latency, Tx=19.2nsec, Rx=44.8nsec.
Minimized resource usage.
Very low price, 1/5 of AMD MAC core.

	DG 10G25GEMAC-IP	AMD 10GEMAC
Tx latency (clk freq.=156.25MHz)	19.2ns (3clk)	19.2ns (3clk)
Rx latency (clk freq.=156.25MHz)	44.8ns (7clk)	115.2ns (18clk)
CLB LUTs	1873	3498
CLB Registers	1072	3291
CLB	326	694

Free bit file for evaluation

DesignGateway provide 1-hour limitation bit file for AMD FPGA Development Boards. You can evaluate UDP100G/40G/25G/10G/1G-IP core on real board before purchasing.