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The Expert of IP Core & Embedded

UDP40G/10G/1G-IP coreUDP/IP stack implementation by all hardware logic

UDP10G-IP

UDP40G/10G/1G IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate UDP10G-IP core on real board before purchasing.


Features

  • All hardware logic to achive CPU-less system
  • Support IPv4 protocol
  • Support one port connection
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • Multicast/broadcast Tx feature customization
  • Super low-latency DG 10G25G EMAC-IP for UDP10G-IP core (Option) Learn more
  • Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
  • Rerference design is included in IP core product

Block diagram


UDP40G-IP
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UDP10G-IP
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UDP1G-IP
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Document & Demo bit file download

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Document name UDP40G/10G/1G-IP
UDP-IP core Presentation Rev1.0XE
UDP-IP core Introduction Video
IP core Introduction

Reference Design Introduction
DG EMAC-IP Presentation (for UDP10G-IP) Rev1.0XE
10G25G EMAC-IP core Introduction Video

Document Name UDP40G-IP UDP10G-IP UDP1G-IP
Datasheet Rev1.1 Rev1.4 Rev1.2
Reference Design Document Rev1.0 Rev1.3 Rev1.1
Demo Instruction Document Rev1.0 Rev2.0 Rev2.0
FPGA Setup Document - Rev3.0 Rev3.0
Evaluation bit file & Apps for PC Get Password ZCU102/ZCU106
KCU105
KCU105
ZCU102
ZC706/KC705/AC701
10G25GEMAC-IP Datasheet - Rev1.3 -


Super low-latency DG 10G25G EMAC IP core

DG 10G25GEMAC core implements the MAC layer for UDP10G-IP core and highly compatible with Xilinx MAC. It has many advantages.

  • Super low-latency, Tx=19.2nsec, Rx=44.8nsec.
  • Minimized resource usage.
  • Very low price, 1/5 of Xilinx MAC core.

DG 10G25GEMAC-IP Xilinx 10GEMAC
Tx latency (clk freq.=156.25MHz) 19.2ns (3clk) 19.2ns (3clk)
Rx latency (clk freq.=156.25MHz) 44.8ns (7clk) 115.2ns (18clk)
CLB LUTs 1873 3498
CLB Registers 1072 3291
CLB 326 694

Free bit file for evaluation

DesignGateway provide 1-hour limitation bit file for Xilinx FPGA Development Boards. You can evaluate UDP40G/10G/1G-IP core on real board before purchasing.


Alliance Partner


Design Gateway Co., Ltd.

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