May 18, 2022

#003 – From RTL IP core to RTL Kernel with Host Application demo

For Turnkey Accelerator System (TKAS-D2101) with Alveo U250 Card and Xilinx Vitis™ Unified Software Platform 2021.1 Based on Xilinx’s Vitis™ Application Acceleration Development Flow Tutorials: bottom_up_rtl_kernel This tutorial introduces a bottom-up Vitis-based RTL kernel construct and wrap-up process, as well as the host-kernel interaction with Xilinx Runtime library (XRT). All the steps in this tutorial use the command-line interface, except...
Categories Accelerated Computing Tutorial
April 20, 2022

#002 Using Multiple DDR Banks

Based on Xilinx’s VitisTM Application Acceleration Development Flow Tutorial: https://github.com/Xilinx/Vitis-Tutorials/tree/2021.2/Hardware_Acceleration/Feature_Tutorials/04-mult-ddr-banks By default, the data transfer between the Kernel and the DDR is accomplished by using single DDR. In some applications, transferring large amount of data between global memory (DDR) and FPGA can be a cause of performance dropped. Using multiple DDR banks can be one of the solutions. Therefore, this...
Categories Accelerated Computing Tutorial