Enhancing Data Reliability in 25G Ethernet Systems with Reed Solomon Forward Error Correction

We delve into the implementation of Reed Solomon – Forward Error Correction in a 25G Ethernet system, with a focus on RS-FEC.  We will be exploring its benefits and practical applications in FPGA-based 25G Ethernet systems.  We will cover the basic concepts of RS-FEC, its implementation on FPGA, and how it enhances data reliability in Ethernet systems.  By the end...

High performance AES256-GCM for secure communication over 100G Ethernet

Secure communication with cryptographic algorithms needs a lot of computation power. Especially, In the Data Center with very high bandwidth networking such as 25G, 100G or more!. Trusted protocols such as TLS and SSL can be processed in real-time at 100Gbps with Hardware Acceleration. AES-GCM is recommended symmetric-key cryptographic block ciphers for TLS and SSL, approved by NIST. Design Gateway’s...

FPGA-based SmartNIC for high-performance TCP/IP application

This article will give you more detail of DG’s TOE100G-IP Core and Silicom’s PacketMover framework and the application of the FPGA-based SmartNIC designed for high performance TCP/IP applications. TOE100G-IP on Silicom’s PacketMover consists of 2 parts This system is the result of a collaboration between Design Gateway and Silicom Denmark.  Using the TOE100G-IP and PacketMover framework, we are proud to present...