DesignGateway Hot! News
December 2017
[ TOE1G/10G IP core ] Accelerates TCP communications, broadcasting and automotive "ALL-TCP/IP"!!
10GbE TCP Off-loading Engine(TOE1G/10G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE1G/10G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design which helps you to reduce development time. DesignGateway provide demo binary file for Xilinx/Intel FPGA boards. You can evaluate TOE1G/10G-IP core on real board before purchasing.

Learn More for Xilinx (TOE10G-IP)
Learn More for Intel (TOE10G-IP)
Xilinx KC705 Demo on Youtube Intel Arria 10 SX Demo on Youtube
Advantages of TOE1G/10G IP
Support both Full Duplex & Half Duplex!!
Over 1200MByte/sec real transfer speed for half-duplex and over 960MByte/sec real transfer speed for full-duplex.
*TOE10G-IP

Enhanced Tx Function
  • Automatic Tx packet generation
  • Acquire MAC address of target by ARP at startup
  • Support both Server and Client mode (Passive/Active open and/or close)
  • Automatic retransmission function by timeout or Duplicate-ACK reception
  • Intelligent flow control by window size detected from ACK packet
  • Able to specify process acceleration by PSH flag enabled in Tx packet.

Sophisticated Rx Function
  • Packet filtering to permit target packet only.
  • Automatic ACK return at ARP receiving
  • Duplicate-ACK transmission by Rx packet error detection
  • Data reordering based on sequence number of Rx packet
  • Window Update packet generation by continuous Rx buffer monitoring

Reduce Cost and Time!
TOE1G/10G IP core include reference design. It helps you to reduce develop time and cost. Free evaluation binary files are available for you to check the performance on real board before purchasing the IP core.
TOE10G IP Presentation for Xilinx TOE10G IP Presentation for Intel
 
TOE1G IP for 1Gbit Ethernet
1Gbit Ethernet Off-loading, All Hardware Logic, without CPU
  • Support both Full Duplex & Half Duplex
  • Support Multi-session
  • Free evaluation on real boards before purchasing
  • Reference design is included in IP core product
TOE1G IP Presentation for Xilinx TOE1G IP Presentation for Intel

News
NVMe IP core supports PCIe Gen3 on Xilinx Zynq Ultrascale+ MPSoC!!
NVMe IP core supports Xilinx Zynq Ultrascale+ MPSoC device and PCIe Gen3 speed. Free evaluation demo on ZCU106 board is available now!! Learn more about NVMe IP core


SATA IP core is available on Alaric Instant-DevKit!!
DesignGateway release SATA-IP core reference design for Alaric Instant-DevKit. You can evaluate the performance of SATA+HOST IP and SATA+HOST with 4ch RAID0 demo with the board now! For more detail SATA-IP Intel page


Technical Updates
Gigabit IP cores

NVMe-IP

SATA-IP

UDP10G-IP

Event
SEMICON JAPAN 2017
Date: Dec 13-15, 2017
Place: TOKYO BIG SIGHT, Japan
More Information

INTERNATIONAL TECHNICAL EXHIBITION ON IMAGE TECHNOLOGY AND EQUIPMENT 2017
Date: Dec 6-8, 2017
Place: PACIFICO YOKOHAMA, Japan
More Information

2017 International Printed Circuit & APEX South China Fair
Date: Dec 6-8, 2017
Place: Shenzhen Convention & Exhibition Center, China
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