
	View on Web Design Gateway Hot! News October 2022 (2)

Fintech AAT demo with Ultra-low Latency Networking IP cores
Available on Turnkey FPGA Accelerator System Solution Learn more for Xilinx \| Learn more for Intel

		DG's Low latency IP demo together with Xilinx's open-source reference design, Accelerated Algorithmic Trading (AAT) is now available on Alveo U50 and U250 Card.
		Reduce latency more than 200ns
Low Latency 10GEMAC-IP (LL10GEMAC-IP)	Low Latency UDP10GRx-IP (LLUDP10GRx-IP)	Low Latency TOE10G-IP (TOE10GLL-IP)
LL10GEMAC-IP Xilinx AAT Demo	LLUDP10GRx-IP 16 Session Demo	TOE10GLL-IP 32 Session Demo

Turnkey FPGA Accelerator System Solution

Design Gateway provides turnkey system with pre-installed AAT (Accelerated Algorithmic Trading) demo using ultra-low latency network IP core. Saving your valuable time on hardware installation and software configuration for Fintech application development.

DG's IP core Solutions for Vertical Market page

DG's IP core Solutions FOR VERTICAL MARKET page to introduces application example by FPGA & DG IPs.Learn more

Technical Updates

The latest Technical Documents Update

NVMe-IP muNVMe-IP for Intel Agilex™ (PCIe Gen4)
TOE100G-IP DMA demo for Alveo card

Events

	Intel® FPGA Technology Day 2022 in Japan
	Design Gateway joins Intel® FPGA Technology Day 2022 in Japan as Gold partner. Date: Nov 15-18, 2021 Place: Online Event Read More (Registration)