Technical & Marketing Document Updates
NVMeTCP-IP ┃NVMe-IP ┃SATA-IP┃QUIC-IP┃TOE-IP┃UDP-IP┃LL Networiking IP┃Security IP┃IPLock┃Turnkey System
※日本語資料のアップデート情報はこちらから (for Japanese)
※日本語資料のアップデート情報はこちらから (for Japanese)
IP core Brochure
| Altera | Gigabit IP core series Brochure for Altera Rev2023Q4 | 2023.11 |
| AMD | Gigabit IP core series Brochure Rev2.6EX | 2020.10 |
DG IP Catalog for Vivado
| AMD | Vivado Design Gateway IP Catalog XML file (2021.12) | 2021.12 |
NVMeTCP-IP
NVMe-IP
NVMeG4-IP | NVMeG3-IP | rmNVMe-IP | muNVMe-IP | raNVMe-IPNVMeG4-IP
| AMD | exFAT2-IP for NVMe IP (Gen4) Datasheet Rev1.0 - New | 2024.5 |
| AMD | exFAT2-IP for NVMe IP (Gen4) Reference Design Document Rev1.0 - New | 2024.5 |
| AMD | exFAT2-IP for NVMe IP (Gen4) Demo Instruction Document Rev1.0 - New | 2024.5 |
| AMD | NVMeG4 IP 2ch RAID0 Reference Design Document Rev1.02 - Updated | 2024.1 |
| AMD | NVMeG4 IP Datasheet Rev2.01 - Updated | 2023.12 |
| AMD | NVMeG4 IP Reference Design Document Rev1.04 - Updated | 2023.12 |
| AMD | NVMeG4 IP Demo Instruction Document Rev1.07 - Updated | 2023.12 |
| AMD | NVMeG4 IP 2ch RAID0 Demo Instruction Document Rev1.3 - Updated | 2023.12 |
| AMD | NVMe IP demo FPGA board Setup Rev4.7 - Updated | 2023.7 |
| AMD | NVMe-IP core series Presentation Rev2.4 - Updated | 2022.10 |
| AMD | NVMeG4 IP 2ch RAID0 Demo Instruction Document Rev1.3 - Updated | 2023.12 |
| AMD | NVMe IP 2ch RAID demo FPGA board Setup Rev2.2 - Updated | 2022.8 |
NVMeG3-IP
rmNVMe-IP
| Altera | rmNVMe IP (Gen5) Datasheet Rev1.0 - New | 2023.8 |
| Altera | rmNVMe IP (Gen5) Reference Design Document Rev1.0 - New | 2023.8 |
| Altera | rmNVMe IP (Gen5) Demo Instruction Document Rev1.0 - New | 2023.8 |
| Altera | rmNVMe IP (Gen4) Datasheet Rev1.0 - New | 2023.6 |
| Altera | rmNVMe IP (Gen4) Reference Design Document Rev1.0 - New | 2023.6 |
| Altera | rmNVMe IP (Gen4) Demo Instruction Document Rev1.1 - Updated | 2023.6 |
| AMD | rmNVMe IP (Gen4) Demo Instruction Document Rev1.1 - Updated | 2023.6 |
| AMD | NVMe IP demo FPGA board Setup Rev4.7 - Updated | 2023.5 |
| AMD | rmNVMe IP (Gen4) Datasheet Rev1.0 - New | 2023.2 |
| AMD | rmNVMe IP Reference Design Document Rev1.0 - New | 2023.2 |
muNVMe-IP
raNVMe-IP
SATA-IP
QUIC-IP
| AMD | QUIC Server 10Gbps IP Datasheet Rev1.00 - New | 2025.3 |
| AMD | QUIC Server 10Gbps IP Reference Design Document Rev1.00 - New | 2025.3 |
| AMD | QUIC Server 10Gbps IP Demo Instruction Document Rev1.00 - New | 2025.3 |
| AMD | QUIC Client 10Gbps IP Datasheet Rev1.00 - New | 2024.7 |
| AMD | QUIC Client 10Gbps IP Reference Design Document Rev1.00 - New | 2024.7 |
| AMD | QUIC Client 10Gbps IP Demo Instruction Document Rev1.00 - New | 2024.7 |
TOExxG-IP series
TOE200G-IP | TOE100G-IP | TOE40G-IP | TOE25G-IP | TOE10G-IP | TOE1G-IP | EMAC-IP| Common | PC software for TOExxG-IP evaluation - New | 2021.9 |
| Altera | TOExxG IP Presentation Rev2.0AE - Updated | 2021.8 |
| AMD | TOExxG IP Presentation Rev2.0XE - Updated | 2021.8 |
TOE200GADV-IP
| Common | TOE200GADV IP Demo Instruction Document Rev1.00 - New | 2024.6 |
| Altera | TOE200GADV IP Datasheet Rev1.00 - New | 2024.6 |
| Altera | TOE200GADV IP Reference Design Document Rev1.00 - New | 2024.6 |
| Altera | TOE200GADV IP FPGA board Setup Rev1.00 - New | 2024.6 |
| AMD | TOE200GADV IP Datasheet Rev1.00 - New | 2024.12 |
| AMD | TOE200GADV IP FPGA board Setup Rev1.00 - New | 2024.12 |
TOE100G-IP / TOE100GADV-IP
TOE40G-IP
| Altera | TOE40G IP Datasheet Rev1.1 - Updated | 2020.10 |
| AMD | TOE40G IP Datasheet Rev1.2 - Updated | 2020.10 |
| AMD | TOE40G IP Demo Instruction Document Rev1.2 - Updated | 2020.3 |
TOE25G-IP
| Common | TOE25G IP 4 Session Demo Instruction Document Rev1.0 - New | 2023.1 |
| Common | TOE25G IP CPU Demo Instruction Document Rev1.3 - Updated | 2022.5 |
| Common | TOE25G IP 2 Port Demo Instruction Document Rev1.0 - New | 2022.5 |
| Altera | TOE25G IP Datasheet Rev1.3 - Updated | 2023.5 |
| Altera | TOE25G IP Reference Design Document Rev1.2 - Updated | 2023.5 |
| Altera | TOE/UDP25G IP demo FPGA board Setup Rev2.2 - Updated | 2023.5 |
| AMD | TOE25G IP Datasheet Rev1.5 - Updated | 2023.5 |
| AMD | TOE25G IP CPU demo Reference Design Document Rev1.4 - Updated | 2023.5 |
| AMD | TOE/UDP25G IP demo FPGA board Setup Rev2.5 - Updated | 2023.5 |
| AMD | TOE25G IP 4 Session Reference Design Document Rev1.0 - New | 2023.1 |
| AMD | TOE25G IP 2 Port demo Reference Design Document Rev1.0 - New | 2022.5 |
| AMD | FTP 25G Server Demo Reference Design Document Rev1.0 - New | 2020.10 |
| AMD | FTP 25G Server demo Instruction Document Rev1.0 - New | 2020.10 |
| AMD | FTP 25G Server demo FPGA board Setup Rev1.0 - New | 2020.10 |
TOE10G-IP
EMAC-IP
| Altera | 10G EMAC IP Datasheet Rev1.2 - Updated | 2021.9 |
| AMD | 10G25G EMAC IP Datasheet Rev1.04 - Updated | 2025.2 |
| AMD | 25GEMAC/PCS+RS-FEC IP Datasheet Rev1.0 | 2023.4 |
| AMD | 25GEMAC/PCS+RS-FEC IP Reference Design Document Rev1.0 | 2023.4 |
| AMD | 25GEMAC/PCS+RS-FEC IP Demo Instruction Document Rev1.0 | 2023.4 |
TOE1G-IP
| Common | TOE1G IP CPU Demo Instruction Document Rev2.02 - Updated | 2025.1 |
| Altera | TOE1G IP Datasheet Rev3.01 - Updated | 2025.3 |
| Altera | TOE/UDP1G IP demo FPGA board Setup Rev2.02 - Updated | 2025.3 |
| Altera | TOE1G IP Reference Design Document Rev2.00 - Updated | 2025.1 |
| Altera | FTP Server Demo Reference Design Document Rev1.0 - New | 2020.2 |
| Altera | FTP Server Demo Instruction Rev1.0 - New | 2020.2 |
| Altera | 2 port Demo Reference Design Document Rev1.0 - New | 2019.12 |
| Altera | 2 port Demo Instruction Document Rev1.0 - New | 2019.12 |
| AMD | TOE1G IP Datasheet Rev3.00 - Updated | 2025.3 |
| AMD | TOE1G IP Reference Design Document Rev2.00 - Updated | 2025.3 |
| AMD | TOE&UDP1G IP demo FPGA board Setup Rev3.01 - Updated | 2025.3 |
| AMD | 2 port Demo Reference Design Document Rev1.4 - Updated | 2023.8 |
| AMD | 2 port Demo Instruction Document Rev1.3 - Updated | 2023.8 |
UDPxxG-IP series
| Common | PC software for UDPxxG-IP evaluation - New | 2021.9 |
| Altera | UDPxxG IP Presentation Rev1.1AE - Updated | 2021.6 |
| AMD | UDPxxG IP Presentation Rev1.1XE - Updated | 2021.6 |
UDP100G-IP
| Common | UDP100G IP Demo Instruction Document Rev1.1 - Updated | 2021.8 |
| Altera | TOE100G/UDP100G IP FPGA board Setup Rev3.2 - Updated | 2023.7 |
| Altera | UDP100G IP Datasheet Rev1.0 - New | 2021.8 |
| Altera | UDP100G IP Reference Design Document Rev1.0 - New | 2021.8 |
| AMD | TOE100G/UDP100G IP FPGA board Setup Rev3.3 - Updated | 2023.5 |
| AMD | UDP100G IP Datasheet Rev1.1 - Updated | 2021.11 |
| AMD | UDP100G IP Reference Design Document Rev1.0 - New | 2021.8 |
UDP40G-IP
| Altera | UDP40G-IP Datasheet Rev1.1 - Updated | 2020.10 |
| AMD | UDP40G-IP Datasheet Rev2.00 - Updated | 2024.3 |
| AMD | UDP40G IP Reference Design Document Rev2.00 - Updated | 2024.3 |
| AMD | UDP40G IP Demo Instruction Document Rev2.00 - Updated | 2024.3 |
| AMD | TOE40G/UDP40G IP FPGA board Setup Rev1.00 - New | 2024.3 |
UDP25G-IP
| Common | UDP25G IP CPU Demo Instruction Document Rev1.0 - New | 2021.6 |
| Altera | TOE/UDP25G IP demo FPGA board Setup Rev2.2 - Updated | 2023.5 |
| Altera | UDP25G IP Reference Design Document Rev1.0 - New | 2021.7 |
| Altera | UDP25G-IP Datasheet Rev1.0 - New | 2021.6 |
| AMD | TOE/UDP25G IP demo FPGA board Setup Rev2.5 - Updated | 2023.5 |
| AMD | UDP25G-IP Datasheet Rev1.1 - Updated | 2023.3 |
| AMD | UDP25G IP Reference Design Document Rev1.1 - Updated | 2023.3 |
UDP10G-IP
| Common | UDP10G IP CPU Demo Instruction Document Rev2.03 - Updated | 2025.3 |
| Altera | UDP10G-IP Datasheet Rev2.00 - Updated | 2025.3 |
| Altera | UDP10G IP Reference Design Document Rev2.00 - Updated | 2025.3 |
| Altera | TOE/UDP10G IP demo FPGA board Setup Rev3.03 - Updated | 2025.3 |
| AMD | UDP10G-IP Datasheet Rev2.00 - Updated | 2025.2 |
| AMD | UDP10G IP Reference Design Document Rev2.00 - Updated | 2025.2 |
| AMD | TOE/UDP10G IP demo FPGA board Setup Rev3.06 - Updated | 2025.2 |
UDP1G-IP
| Common | UDP1G IP CPU Demo Instruction Document Rev2.01 - Updated | 2025.3 |
| Altera | UDP1G IP Datasheet Rev2.00 - Updated | 2025.3 |
| Altera | TOE/UDP1G IP demo FPGA board Setup Rev2.02 - Updated | 2025.3 |
| Altera | UDP1G IP Reference Design Document Rev2.00 - Updated | 2025.3 |
| AMD | TOE&UDP1G IP demo FPGA board Setup Rev3.01 - Updated | 2025.3 |
| AMD | UDP1G-IP Datasheet Rev1.2 - Updated | 2020.10 |
Low Latency Networking IP
TLS1.3 IP
| AMD | TLS1.3 Client 10Gbps IP Datasheet 1.04 - Updated | 2025.4 |
| AMD | TLS1.3 Client 10Gbps IP Reference DesignDocument Rev1.03 - Updated | 2025.4 |
| AMD | TLS1.3 Client 10Gbps IP Demo Instruction Document 1.03 - Updated | 2025.5 |
| AMD | TLS1.3 Client 10Gbps IP Reference DesignDocument for KR260 Rev1.00 - New | 2025.3 |
| AMD | TLS1.3 Client 10Gbps IP Demo Instruction Document KR260 1.00 - New | 2025.3 |
| AMD | TLS1.3 Server 10Gbps IP Datasheet 1.00 - New | 2024.3 |
| AMD | TLS1.3 Server 10Gbps IP Reference DesignDocument Rev1.00 - New | 2024.3 |
| AMD | TLS1.3 Server 10Gbps IP Demo Instruction Document 1.00 - New | 2024.3 |
AES256-XTS IP
| Altera | AES256-XTS-STG IP Datasheet 1.00 - Updated | 2023.9 |
| Altera | AES256-XTS-STG IP with NVMe IP Reference Design Document Rev1.01 - New | 2023.9 |
| Altera | AES256-XTS-STG IP Reference Design Document Rev1.00 - New | 2023.8 |
| Altera | AES256-XTS-STG IP Demo Instruction Document 1.00 - New | 2023.8 |
| Altera | AES256-XTS IP Datasheet 1.01 - Updated | 2023.2 |
| Altera | AES256-XTS IP Reference Design Document Rev1.00 - New | 2022.11 |
| Altera | AES256-XTS IP Demo Instruction Document 1.00 - New | 2022.11 |
| AMD | AES256-XTS-STG IP with NVMe IP Reference Design Document Rev1.03 - Updated | 2025.4 |
| AMD | AES256-XTS-STG IP Datasheet 1.01 - Updated | 2024.5 |
| AMD | AES256-XTS-STG IP Demo Instruction Document 1.01 - Updated | 2024.5 |
| AMD | AES256-XTS-STG IP Reference Design Document Rev1.00 - New | 2023.8 |
| AMD | AES256-XTS IP Datasheet 1.01 - Updated | 2023.2 |
| AMD | AES256-XTS IP Reference Design Document Rev1.00 - New | 2022.11 |
| AMD | AES256-XTS IP Demo Instruction Document 1.00 - New | 2022.11 |
AES256-GCM IP
AES128/256-IP
SHA2-IP
(SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, SHA-512/256)| Altera | SHA2 IP Datasheet 1.00 - New | 2025.4 |
| Altera | SHA2 IP Reference Design Document 1.00 - New | 2025.4 |
| Altera | SHA2 IP Demo Instruction Document 1.00 - New | 2025.4 |
| AMD | SHA2 IP Datasheet 1.00 - New | 2025.4 |
| AMD | SHA2 IP Reference Design Document 1.00 - New | 2025.4 |
| AMD | SHA2 IP Demo Instruction Document 1.00 - New | 2025.4 |
SHA256-IP
| Altera | SHA256 IP Datasheet 1.00 - New | 2021.1 |
| Altera | SHA256 IP Demo Instruction Document 1.00 - New | 2021.1 |
| AMD | SHA256 IP Datasheet 1.00 - New | 2025.3 |
| AMD | SHA256 IP Demo Instruction Document 1.00 - New | 2025.3 |
tCAM-IP
| Altera | tCAM IP Search Replace Demo Reference Design Document for Agilex 7 I-series 1.00 - New | 2023.7 |
| Altera | tCAM IP Search Replace Demo Instruction Document for Agilex 7 I-series 1.00 - New | 2023.7 |
| Altera | tCAM IP Datasheet 1.02 - Updated | 2021.3 |
| Altera | tCAM IP Search Replace Demo Reference Design Document 1.02 - Updated | 2021.3 |
| Altera | tCAM IP Search Replace Demo Instruction Document 1.00 - New | 2021.1 |
| Altera | Presentation Rev1.0 - New | 2020.11 |
| Altera | tCAM IP Reference Design Document Rev1.00 - New | 2020.8 |
| AMD | tCAM IP Datasheet Rev2.00 - Updated | 2024.10 |
| AMD | tCAM IP Reference Design Document Rev2.01 - Updated | 2024.10 |
| AMD | tCAM IP Demo Instruction Document Rev2.01 - Updated | 2024.10 |
| AMD | UDP Packet Switching Reference Design Document Rev1.00 - New | 2024.10 |
| AMD | UDP Packet Switching Demo Instruction Rev1.01 - New | 2024.10 |
| AMD | Presentation Rev1.0 - New | 2021.8 |
IPLock
| Common | How to transfer design with IPLock from ISE to Vivado - New | 2022.4 |
Turnkey System
| AMD | Accelerated Algorithmic Trading (AAT) Demo Instruction Rev1.1 - Updated | 2022.9 |
| AMD | Getting Started with Turnkey Accelerator Systems TKAS-D2101 - New | 2021.11 |
| AMD | Presentation Rev1.0XE - New | 2021.10 |
| AMD | Turnkey System TKAS series Product Leaflet - New | 2021.8 |
| Jan | Feb | Mar | Apr | May | Jun | Jul | Aug | Sep | Oct | Nov | Dec | 1 year |
Alliance Partner
Design Gateway Co., Ltd.
Head Office3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
89/26 Amornpan 205 Tower1, 18th floor, Ratchadapisek7 (Nathong) Alley, Ratchadapisek Road, Din Daeng, Bangkok, 10400 THAILAND
AI Lab
Faculty of Engineering, Chulalongkorn University, 12th floor, Engineering 4 Building (Charoenvidsavakham), Phayathai Rd., Wang Mai, Pathumwan, Bangkok, 10330 THAILAND
