rmNVMe-IP for Gen5: Breakthrough 4K IOPS Performance with fully CPU offload

Experience groundbreaking 4K IOPS performance with the rmNVMe-IP Gen5 storage IP core! Say goodbye to CPU bottlenecks as this innovative core offers fully CPU offloaded operations. Achieve mind-blowing data transfer speeds exceeding 10,000 MB/s write speed, effortlessly. Discover simplified NVMe Gen5 SSD random access with minimal signal usage. This demo showcases key features like simultaneous 4KB read and write command...

Demonstration of very high throughput and highly secure TLS transmission with DG’s TLS1.3 IP-Core

Join us for an exciting showcase of our Transport Layer Security (TLS) solution! In this demo, we highlight the utilization of DG’s security IP-core, including AES256GCMIP, to establish a secure connection using the TLS1.3 protocol. Experience how TLS1Gdemo, designed as a client, seamlessly connects with HTTP/HTTPS servers like Node.js. Witness the demo system in action, comprising a server, web browser,...

Enhancing TLS Data Security and Performance with DG’s TLS1.3 IP-Core

Join us as we delve into the world of Transport Layer Security (TLS). In this article, Discover the importance of TLS, its role in securing connections, and how it works. We explore the TLS1.3 protocol, which offers enhanced encryption, authentication, and integrity to safeguard sensitive information from potential hackers. Learn about the risks of unsecured connections and how TLS mitigates...

The Enhanced Xilinx’s Stock Trading (AAT) demo by integrating DG’s Low-Latency IP Cores

Join us for an exciting demo of Xilinx’s Accelerated Algorithmic Trading (AAT) system, powered by Design Gateway’s low-latency IP core suites. Experience the competitive advantage of significantly reduced latency times, accelerating stock trading. This demo seamlessly runs on Alveo U50 and U250 cards, integrating the super low-latency 10G EMAC (LL10GEMAC), UDP (UDP10GRxIP), and TOE (TOE10GLLIP). Follow the step-by-step setup guide...

Breaking Latency Barriers in Stock Trading with AMD Xilinx AAT and DG Low-Latency IP Cores

Join us in this exciting article where we showcase the integration of our Low-latency network IP suites with AMD Xilinx’s cutting-edge Accelerator Card and the Accelerated Algorithmic Trading system, AAT. Discover how this integration revolutionize1s the FinTech industry by overcoming latency limitations, specifically in High-Frequency Trading (HFT) applications. We delve into the primary application of the Trade Engine in HFT,...

Enhancing Data Reliability in 25G Ethernet Systems with Reed Solomon Forward Error Correction

We delve into the implementation of Reed Solomon – Forward Error Correction in a 25G Ethernet system, with a focus on RS-FEC.  We will be exploring its benefits and practical applications in FPGA-based 25G Ethernet systems.  We will cover the basic concepts of RS-FEC, its implementation on FPGA, and how it enhances data reliability in Ethernet systems.  By the end...