DesignGateway Hot! News December 2016

	[ SDLink ] Easy update of configuration data after FPGA product shipment!
	SDLink is a high speed FPGA configuration module which stores data on microSD card. FPGA configuration data is easily updated by just swapping microSD card. More detail SDLink Demo video clip on Youtube

Easy to update the circuit by swapping microSD!! [For Developers] More easy to Evaluate various circuit patterns! If you prepare multiple microSD cards and program deferent configuration data, you can evaluate and test these circuit patterns without suspending to re-program. Your development will be drastically faster!! More detail No Need Programming tools No Need Download Cable No Need System suspended [For Product updates] More quickly to mass-product updates! Just to swap microSD card to update the circuit data immediately. Because you do not need to program to board directly anymore, you can quickly support circuit modification, update and change setting after delivery. More detail More detail about Usability of SDLink News [ NVMe IP ] BRAM version coming!! NVMe-IP core is epochally improved to support BRAM operation without external memory such as DDR. Release and support information will be released from Jan 2017. More information for Xilinx More information for Altera Technical Updates NVMe-IP Xilinx NVMe IP Presentation Rev1.4 - Updated SATA-IP Altera SATA Host IP Datasheet Rev1.1 - Updated SATA Host IP Reference Design Document Rev1.0 - New SATA Host IP Demo Instruction Document Rev1.1 - Updated SATA Host IP RAID0 Reference Design Document Rev1.0 - New SATA Host IP RAID0 Demo Instruction Document Rev1.0 - New Xilinx SATA Host IP Datasheet Rev1.2 - Updated SATA Host IP Reference Design Document Rev1.2 - Updated SATA Host IP Demo Instruction Document Rev1.4 - Updated SATA Host IP RAID0 Reference Design Document Rev1.3 - Updated SATA AHCI IP Datasheet Rev1.4 - Updated TOE10G-IP Altera TOE10G IP Multi-Session Reference Design Document Rev1.0 - New TOE10G IP Multi-Session Demo Instruction Document Rev1.0 - New Xilinx TOE10G IP Multi-Session Reference Design Document Rev1.0 - New TOE10G IP Multi-Session Demo Instruction Document Rev1.0 - New TOE1G-IP Xilinx TOE1G IP Datasheet Rev2.5 - Updated TOE1G IP Reference Design Document Rev1.4 - Updated TOE1G IP Demo Instruction Document Rev1.6 - Updated TOE1G IP Full Duplex Demo Instruction Document Rev1.4 - Updated Event SEMICON JAPAN 2016 Date : 14 - 16 December 2016 10:00 - 17:00 Place : Tokyo Big Sight, Tokyo Japan More Information 46th NEPCON JAPAN Date : 18 - 20 Jan 2017 10:00 - 18:00 Place : Tokyo Big Sight, Tokyo Japan More Information 2016 International Printed Circuit & APEX South China Fair Date : 7 - 9 Dec 2016 Place : Shenzhen Convention & Exhibition Center, China More Information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga_E.html 発行者 DesignGateway Co., Ltd. http://www.design-gateway.com/ Mail：ip-sales@design-gateway.com | About Us| Contact| (c) 2016 Design Gateway Co., Ltd.