Design Gateway Hot! News October 2020

CPU-less Super High-speed Network Storage by DG IP core Solutions!!
Design Gateway provides both CPU-less high-speed networking and CPU-less storage solutions. You can build a super high-speed practical application by combining DG IP core solutions.
Design Gateway can provide CPU-less super high-speed network storage reference design. This design implements TOE10G-IP, NVMe-IP and exFAT-IP, and it achieved ultra-fast file uploading and downloading over 1GB/sec on Xilinx KCU105. By replacing with TOE25G-IP/TOE40G-IP and NVMeG4-IP, it will be able to achieve more high-speed network storage.	Ultra high-speed FTP Server Performance demo video on YouTube
TOE10G FTP Server Demo Reference Design Document for Xilinx
TOE10G IP for Xilinx	TOE10G IP for Intel
NVMe IP for Xilinx	NVMe IP for Intel

News

	NVMe IP and TOE25G IP for Intel Stratix 10 GX
	Learn more about NVMe-IP for Intel Learn more about TOE25G-IP for Intel

	The article of tCAM IP on Intel Inside Edge
	You can read the article of tCAM-IP core on Intel Inside Edge in September 2020 The tCAM-IP can make deterministic search at 200MSPS continuously speed with constant latency at 7 clock cycles on Intel Arria 10 SX. Read Intel Inside Edge Learn more about tCAM-IP

	The article of NVMeG4 IP on Xilinx Community Forums
	Xilinx Community Forums Blog page introduces NVMeG4-IP core. NVMeG4-IP core by Leveraging Xilinx's UltraScale+ GTY Transceivers. Read Xilinx Community Forums Blog Learn more about NVMeG4-IP

New YouTube Videos Subscribe to DG IP core YouTube channel Gigabit IP cores achieve ultra high-speed performance on Intel FPGAs (Japanese) TOE25G IP core Performance Demo on Intel Stratix 10 GX Technical Updates IP core Brochure Intel Gigabit IP core series Brochure Rev2.6EA - Updated Xilinx Gigabit IP core series Brochure Rev2.6EX - Updated NVMe-IP Intel NVMe IP for Stratix 10 Datasheet Rev1.0 - New NVMe IP for Stratix 10 Reference Design Document Rev1.0 - New NVMe IP demo FPGA board Setup Rev4.1 - Updated TOE40G-IP Intel TOE40G IP Datasheet Rev1.1 - Updated Xilinx TOE40G IP Datasheet Rev1.2 - Updated TOE25G-IP Intel TOE25G IP Datasheet Rev1.0 - New TOE25G IP Reference Design Document Rev1.0 - New TOE25G IP demo FPGA board Setup Rev1.0 - New TOE10G-IP Intel TOE10G IP Datasheet Rev1.6 - Updated Xilinx TOE10G IP Datasheet Rev1.13 - Updated EMAC-IP Intel 10G EMAC IP Datasheet Rev1.1 - Updated TOE1G-IP Intel TOE1G IP Datasheet Rev2.10 - Updated Xilinx TOE1G IP Datasheet Rev2.9 - Updated UDP40G/10G/1G-IP Intel UDP40G-IP Datasheet Rev1.1 - Updated UDP10G-IP Datasheet Rev1.2 - Updated UDP1G-IP Datasheet Rev1.4 - Updated Xilinx UDP40G-IP Datasheet Rev1.1 - Updated UDP10G-IP Datasheet Rev1.4 - Updated UDP1G-IP Datasheet Rev1.2 - Updated Events CEATEC 2020 Date : Oct 20-23, 2020 Venue : Online More Information AI & BUSINESS AUTOMATION EXPO Date : Oct 28-30, 2020 Venue : Makuhari Messe, Japan More Information IOT & 5G SOLUTIONS EXPO Date : Oct 28-30, 2020 Venue : Makuhari Messe, Japan More Information DATA CENTER & STORAGE EXPO Date : Oct 28-30, 2020 Venue : Makuhari Messe, Japan More Information 2020 TAITRONICS Date : Oct 21-23, 2020 Venue : Taipei Nangang Exhibition Center, Taipei, Taiwan More Information KES 2020 Date : Oct 27-30, 2020 Venue : COEX, Korea More Information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga_E.html Publisher DesignGateway Co., Ltd. http://www.design-gateway.com/ Contact Us | About Us| Contact| (c) 2020 Design Gateway Co., Ltd.