AES256-XTS IP High throughput & Super Low Latency for secure storage applications
AES256-XTS-STG IP implement the advanced encryption standard (AES) with XEX (XOR Encrypt XOR) tweakable block cipher which operates sequences of complete blocks and is widely used in protecting the confidentiality of data on various storage devices with interfaces such as NVMe and SATA. We also have a lineup of "2X" ideal for NVMe PCIe Gen4, and "4X", supported Gen5.
Key Features
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Block diagram * Click to show more detail YouTube Video Enhancing NVMe SSD Security with AES256-XTS-STG Encryption |
Technical Documents
| Documents | Altera |
| AES256-XTS-STG IP Datasheet | Rev1.00 |
| AES256-XTS-STG IP Reference Design Document | Rev1.00 |
| AES256-XTS-STG IP with NVMe-IP Reference Design Document | Rev1.01 |
| Demo Instruction Document | Rev1.00 |
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| Free Evaluation Demo file | |
| AES256-XTS-STG IP (for NVMe Gen3) | Arria® 10 SX |
| AES256-XTS-STG-2X IP (for NVMe Gen4) | |
| AES256-XTS-STG-4X IP (for NVMe Gen5) | Agilex™ I-series |
| AES256-XTS-STG IP (with NVMe Gen3 IP) | Arria® 10 SX |
| AES256-XTS-STG-2X IP (with NVMe Gen4 IP) | |
| AES256-XTS-STG-4X IP (with NVMe Gen5 IP) | Agilex™ I-series |
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| Free Evaluation Project | |
| AES256-XTS-STG IP (for NVMe Gen3) | Github  |
| AES256-XTS-STG-2X IP (for NVMe Gen4) | Github |
| AES256-XTS-STG-4X IP (for NVMe Gen5) | Github |
AES256-XTS IP core implement the advanced encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing (XTS) which is widely used in protecting the confidentiality of data on storage devices.
Key Features
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Block diagram * Click to show more detail YouTube Video AES256-XTS IP Introduction & Demo |
Technical Documents
| IP core | Datasheet | Reference Design Document | Design Guide | Demo Instruction Document | Free Evaluation Demo file |  |
| AES256-XTS IP | Rev1.01 | Rev1.00 | Rev1.00 | Rev1.00 | Agilex™ F-series Arria® 10 SX |
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For pricing and licensing terms, please contact us.
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