本文へスキップ

The Expert of IP Core & Embedded

|

CPU-less TLS1.3 Offload IP core for FPGA Acceleration

Features┃Block diagram┃Document Download┃Performance Comparison┃Applications
TLS1.3-IP

TLS1.3 IP (Transport Layer Security IP) is the CPU-less & High-performance TLS v1.3 protocol engine for FPGA Acceleration with no CPU and external memory required. Providing maximum Gigabit Ethernet throughput for highly secure data transmission over 1G/10G/25G/100G network. Protect your valuable data from potential security breaches by using TLS secure transmission now! Especially, in Industrial IoT & Automation, Aerospace & Defense Applications.

Our TLS 1.3 IP core demo can successfully demonstrate very high throughput HTTPS Upload and Download with standard web server by pure hardware logic on FPGA.

Features

  • Support TLS1.3 cipher suite: TLS_AES_256_GCM_SHA384
    • Key exchange : X25519
    • Derive key : HKDF with SHA384
    • Encryption/decryption : AES256GCM
  • Signature algorithm:
    • rsa_pss_rsae_sha256 with 2048-bit RSA public key
    • ecdsa_secp256r1_sha256
  • Recommended Clock Frequency: At least 180 MHz for maximum throughput
  • Customized service for following features
    • Maximum fragment length and buffer size extension
    • Certificate size extension
  • Listed in the AMD Adaptive Computing Partner Solutions

Block diagram

TLS1.3 IP Block Diagram
* Click to show more detail

Document download

Technical document update page

Technical Documents

Support Devices Zynq UltraScale+ ZCU106, ZCU102, Kintex Ultrascale+ KCU116 | for other device, please contact us
IP core Datasheet Reference Design Document Demo Instruction Document Free Evaluation demo file
TLS 1.3 Server 10G IP
(TLS10GS-IP)		 Rev1.01 Rev1.01 Rev1.01 ZCU102
TLS 1.3 Client 10G IP
(TLS10GC-IP)		 Rev1.06 Rev1.05 Rev1.05 ZCU106
KCU116
 KR260 KR260 Github
TLS 1.3 Client
1G IP		 Rev1.01 AC701

Performance Comparison

TLS1.3 Server 10G IP

TLS1.3 Server IP Performance
* Click to show more detail

TLS1.3 Client 10G IP

TLS1.3 Client IP Performance
* Click to show more detail

Free Bit file for evaluation

Free evaluation demo is available on AMD FPGA boards. Download

Demo Instruction & Video:

Application example

Aerospace Telemetry

Ensure the integrity and confidentiality of sensitive inflight data streams from remote sensors in aerospace applications. FPGA-accelerated TLS 1.3 outpaces software-only solutions, safeguarding critical flight information. Read more

Medical Device Connectivity

Protect patient data in transit between medical devices and healthcare systems. Our solution provides the robust encryption and authentication mechanisms needed to comply with stringent healthcare regulations and safeguard patient privacy. Read more

About price and licence of the IP core, please contact Design Gateway.


Alliance Partner


Design Gateway Co., Ltd.

Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN

R&D
89/26 Amornpan 205 Tower1, 18th floor, Ratchadapisek7 (Nathong) Alley, Ratchadapisek Road, Din Daeng, Bangkok, 10400 THAILAND

AI Lab
Faculty of Engineering, Chulalongkorn University, 12th floor, Engineering 4 Building (Charoenvidsavakham), Phayathai Rd., Wang Mai, Pathumwan, Bangkok, 10330 THAILAND