Design Gateway's Technology Blog – Page 6 – The Expert of IP Core & Embedded Systems

February 28, 2023

FPGA-based SmartNIC for high-performance TCP/IP application

This article will give you more detail of DG’s TOE100G-IP Core and Silicom’s PacketMover framework and the application of the FPGA-based SmartNIC designed for high performance TCP/IP applications. TOE100G-IP on Silicom’s PacketMover consists of 2 parts This system is the result of a collaboration between Design Gateway and Silicom Denmark. Using the TOE100G-IP and PacketMover framework, we are proud to present...

Networking

February 20, 2023

rmNVMe-IP (Random Access & Multi User NVMe IP) : Demo & Performance

rmNVMe-IP (Random Access & Multi User NVMe IP) is very high performance NVMe Host Controller which is highly optimized for high-IOPS random access applications. rmNVMe-IP supports multiple user interfaces, each user can simultaneously read/write to a single NVMe SSD at the same time. This is the demo & performance to show you how to setup and run our demo to...

Storage

February 14, 2023

rmNVMe-IP (Random Access & Multi User NVMe IP) : Application

rmNVMe-IP (Random Access & Multi User NVMe IP) is very high performance NVMe Host Controller which is highly optimized for high-IOPS random access applications. rmNVMe-IP supports multiple user interfaces, each user can simultaneously read/write to a single NVMe SSD at the same time. This is the example application of rmNVMe-IP Core. rmNVMe-IP Core consist of 3 parts Please check the...

Storage

February 10, 2023

rmNVMe-IP (Random Access & Multi User NVMe IP) : Introduction

rmNVMe-IP (Random Access & Multi User NVMe IP) is very high performance NVMe Host Controller which is highly optimized for high-IOPS random access applications. rmNVMe-IP supports multiple user interfaces, each user can simultaneously read/write to a single NVMe SSD at the same time. This is the introduction to explain the concept and features of rmNVMe-IP Core. rmNVMe-IP Core consist of...

Storage

January 31, 2023

2X performance increase with RAID0x2 by muNVMe-IP Core

muNVMe-IP (Multi User NVMe IP) is designed and optimized for multiple data stream access to single NVMe SSD by multiple users simultaneously. RAID0x2 by muNVMe-IP module in this reference design are designed to split one user command to two muNVMe-IPs. The RAID0x2 module is implemented to increase the sequential write/read performance to 2 times(2X), comparing to the muNVMe-IP reference design....

Storage

January 23, 2023

AES-XTS for Automotive

In automotive applications, AES-XTS is used to encrypt data stored on a vehicle’s internal storage devices, such as infotainment systems and navigation systems. This helps to protect sensitive information, such as personal data, navigation data, and vehicle settings, from being accessed by unauthorized parties. What’s AES-XTS? AES-XTS is a mode of operation for AES encryption that is designed for disk...

Security

December 9, 2022

Moving Average Accelerator (Real-time data stream processing)

This example demonstrate a free-running kernel. Free-running kernel is a kernel which always repeatedly execute on its own whearas normal kernel requires user command (such as q.enqueueTask(krnl)). One scenario one might use a free-running kernel is processing a data stream from other kernel (both RTL/HLS) without any CPU involvement. Configuration File These lines specify which kernels are instantiated and how many....

HLS Development Series

December 9, 2022

2D Perlin Noise Generator Accelerator

This is simple example that generate 2D perlin noise in FPGA and write the values to a file as python style lists. The main aim of this example is to introduce the DATAFLOW pragma which enable task level parallelism. However, the main purpose of using DATAFLOW pragma is to show how writing HLS C++ code for hardware generally requires a...

HLS Development Series

December 9, 2022

MD5 Computation Accelerator

This is a simple example demonstrating how to use FPGA hardware accerleration by writing C++ codes. This example is only intended to show how to write simple algorithms in C++ and them in FPGA without much consideration for performance. Thus, the md5 implementation in this example will be very straight forward and similar to how one might normally implement md5...

HLS Development Series

November 25, 2022

Super-resolution on KV260

The Kria KV260* is one of Xilinx edge devices designed to be suitable for Vision AI based applications.To implement customized AI applications on KV260, Xilinx Vitis AI** is used as a development stack to develop AI inference. It consists of optimized IP, tools, libraries, example designs, and free pre-trained models. For super resolution application, Vitis AI model zoo provides a...

FPGA & AI