Achieving Zero-CPU 10GbE TCP/UDP Offload on Agilex 9 Direct RF-Series
Modern radar, electronic warfare (EW), signal intelligence (SIGINT), and high-speed sensor systems generate enormous amounts of RF data. For systems using the Altera Agilex™ 9 Direct RF-Series, moving this data without creating a bottleneck is critical.
Standard Software Stack
- Consumes valuable processor resources.
- Creates potential bottlenecks for high-speed RF data.
- Takes resources away from system control and app tasks.
TOE10G-IP / UDP10G-IP
- Network protocol processing implemented directly in FPGA hardware.
- Enables a fully CPU-free 10 Gigabit Ethernet data path.
- Presents application logic with a simple 64-bit FIFO interface.
Agilex 9 Reference Demo Performance
~1,200 MB/s
Approaching the practical payload limit of a 10GbE connection
🎥 Watch the Full Demonstration
See TOE10G-IP and UDP10G-IP running on real Agilex 9 hardware, including FPGA-to-FPGA TCP and UDP data transfers at approximately 1,200 MB/s.
See the full demo: TOE10G-IP and UDP10G-IP On Agilex 9
🔍 Why Hardware-Based Network Offloading?
While software network stacks provide flexibility, high-speed networking can severely increase processor workload. Moving these functions to hardware provides a clear advantage for applications that continuously generate high-volume data.
Reduce Processor Workload
Eliminates the heavy CPU burden caused by packet processing, buffering, memory movement, interrupts, and protocol management in conventional embedded systems.
Simplify the Data Path
Design Gateway’s IP cores process the network protocol directly in FPGA logic, allowing the application to focus exclusively on handling payload data.
Deterministic Performance
The ideal architecture for systems where high throughput, deterministic hardware processing, and highly efficient FPGA-to-network data movement are critical.
🔧 TOE10G-IP: Reliable 10GbE Data Transfer
When reliable data delivery is the priority, TCP is the preferred protocol. TOE10G-IP provides an FPGA-native networking solution for systems needing high throughput together with TCP’s ordered delivery.
10GbE Practical Limit
Transfers TCP payload data at ~1,200 MB/s (9.6 Gbit/s), maximizing the practical throughput of a 10GbE connection.
Zero CPU Overhead
Implements TCP/IP processing directly in FPGA logic, eliminating the need for an application processor in the data path.
Straightforward Interface
The IP handles complex TCP functions automatically, leaving user logic to transfer payload via a simple 64-bit FIFO interface.
Typical Applications
Command and control
Mission data recording
High-speed file transfer
Remote storage
FPGA-to-FPGA / PC communication
Lossless sensor data
🔧 UDP10G-IP: Lightweight High-Speed Streaming
Not every application requires TCP. For real-time streaming where low overhead and continuous data delivery are prioritized over retransmission, UDP provides a better fit.
High-Speed Performance
Reaches ~1,200 MB/s throughput (Agilex 9 demo), moving massive data volumes across a 10GbE network.
Hardware Processing
Processes UDP/IP packets directly in FPGA logic using a simple data interface—no software stack needed.
Lightweight Architecture
Eliminates TCP connection management and flow-control overhead for streaming-oriented applications.
Typical Applications
Real-time RF data streaming
Radar data transfer
Sensor streaming
Live monitoring
High-speed data acquisition
FPGA-to-FPGA streaming
Long-distance transmission
🧭 TOE10G-IP or UDP10G-IP: Which Should You Use?
The choice depends primarily on whether your application prioritizes reliable delivery or low-overhead streaming.
| Feature | TOE10G-IP | UDP10G-IP |
|---|---|---|
| Protocol | TCP/IP | UDP/IP |
| Maximum demonstrated throughput | ~1,200 MB/s | ~1,200 MB/s |
| Data delivery | Reliable and ordered | Best-effort |
| Retransmission | Supported by TCP | Not provided by UDP |
| User data interface | Simple 64-bit FIFO | Simple 64-bit FIFO |
| CPU required in high-speed data path | No | No |
| Approximate logic size* | ~2,700 ALMs | ~1,700 ALMs |
| Best suited for | Reliable transfer, file/data transfer, control | Real-time streaming, RF/sensor data |
* FPGA resource utilization depends on the selected FPGA device, configuration, buffer settings, Ethernet interface, synthesis conditions, and surrounding logic. These figures should be treated as reference values rather than fixed utilization for every implementation.
⚙️ System Architecture on Agilex 9 Direct RF-Series
To demonstrate the solution on real hardware, Design Gateway implemented the TOE10G-IP and UDP10G-IP solutions on an Altera Agilex 9 Direct RF-Series platform.
In the reference architecture, the FPGA connects to a remote endpoint through a 10 Gigabit Ethernet link. The remote endpoint can be another FPGA platform or a PC, depending on the final system architecture. The Ethernet connection may also be configured as a direct point-to-point link or incorporated into a standard Ethernet network.
The high-speed protocol processing remains within the FPGA fabric while the application logic exchanges payload data through the IP core’s simple user data interface.
🚀 TOE10G-IP Hardware Demo
Two FPGA platforms communicate through a 10GbE connection to demonstrate direct hardware TCP/IP protocol processing without developing a complete stack from scratch.
~1,200 MB/s
Throughput
🚀 UDP10G-IP Hardware Demo
A parallel setup demonstrating a high-throughput UDP data path suitable for continuous data-streaming applications from FPGA logic onto a 10GbE network.
~1,200 MB/s
Throughput
Final Takeaway
While the Agilex 9 Direct RF-Series excels at RF conversion and FPGA processing, moving that data efficiently to storage or monitoring systems is equally critical. Design Gateway’s IP cores bridge this gap by providing a seamless, hardware-based network offload layer.
Achieve ~1,200 MB/s throughput to maximize 10GbE bandwidth.
Integrate instantly via a simple payload interface without building protocol stacks.
Maintain a CPU-free, high-speed data path directly in hardware.
Choose TOE10G-IP
Deploy when reliable TCP communication and guaranteed data delivery are the absolute priority.
Choose UDP10G-IP
Deploy when a lightweight, high-speed real-time streaming path is required.
📩 Contact Us
If you are developing an FPGA-based radar, electronic warfare, signal intelligence, RF data-acquisition, or other high-speed networking system and would like to discuss the suitable Design Gateway IP core solution for your application, please contact Design Gateway for more information.
📚 Learn More About TOE10G-IP and UDP10G-IP
Explore the related Design Gateway product pages and technical documents for detailed specifications, interface information, supported FPGA families, and reference-design options.
🧪 Free Evaluation File
Start your evaluation with Design Gateway reference designs and demo environments prepared for supported FPGA platforms. Evaluation resources can help you confirm IP core functionality, interface behavior, and achievable performance before moving to full product integration.
Accelerate your development. Download free reference designs and out-of-the-box demo environments for our 10G IP cores.
TOE10G-IP Demos
UDP10G-IP Demos
🤝 Official Partner Platform Availability
Design Gateway IP core solutions are available for major FPGA platforms, including Altera FPGA devices. For this demonstration, we implemented the TOE10G-IP and UDP10G-IP on the Altera Agilex 9 Direct RF-Series platform.
