Hardware-Accelerated Multi-Algorithm SHA3 Hashing Engine for FPGAThe SHA3 IP core implements all six algorithms defined in FIPS PUB 202 — SHA3-224, SHA3-256, SHA3-384, SHA3-512, SHAKE128, and SHAKE256 in a single unified core, delivering over 17.5 Gbps throughput. Proven with a working hardware demo on the AMD Kria KR260 evaluation board. |
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SHA3 IP Key Features
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SHA3 IP YouTube Video |
SHA2 IP core supports SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224, and SHA-512/256 secure hash algorithms. The core is fully compliant with the FIPS PUB 180-4 (Federal Information Processing Standard) specification. Suitable for applications such as secure communication, password authentication, and blockchain data integrity. |
SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 1.575 Gbps throughput @ 200MHz. |
SHA2 IP Key Features
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SHA-256 IP Key Features
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SHA2 IP Block diagram
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SHA-256 IP YouTube Video![]() SHA-256 IP Introduction |
| IP core | Datasheet | Reference Design Document | Demo Instruction Document | Free Evaluation Demo file |
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![]() SHA3 IP |
KR260 | ||||
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![]() SHA2 IP |
KCU116 | ||||
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![]() SHA-256 IP |
KCU105 | ![]() |
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