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USB3.0-IP coreHost side just released!!

USB3.0-IP

USB3.0-IPcore compliants with the USB 3.0 specification Revision1.0 and work on Xilinx 7-Series, Spartan-6 and Virtex-6 device.
This IPcore provide link layer and protocol layer. Physical layer interfaces to PHY chip by TI.
DesignGateway provide 1-hour limited bit file for Xilinx evaluation boards. You can evaluate on Xilinx FPGA boards before purchasing the IPcore.



Features

  • Compliant with the USB3.0 specification Revision1.0
  • USB3.0 Host or Device Controller
  • Implement link layer and protocol layer
  • Physical layer interfaces to PHY chip by TI
  • IP core clocks are adjustable (250MHz for PIPE I/F, more than 125MHz for internal)
  • Support 16bit PIPE interface
  • Support IN/OUT end point up to 15 points
    - 1 point for control
    - 7 points each for IN/OUT
  • Support All transmission taps (Control, Bulk, Isochronous and Interrupt transmission)
  • Simple transaction interface with Host processor or DMA interface
  • Able to evaluate on ML605/SP605/KC705/ZC706 board before purchasing the IP core
  • Go to Registration page to get password

Block diagram (Host side)



Document download

Common Documents

Document name Download
USB3.0-IP core Presentation Rev1.7
FAT32 Data Recorder Presentation Rev1.0
AB07-USB3FMC Board Manual Rev1.2

Document name Zynq-7000
ZC706
Kintex-7
KC705
Spartan-6
SP605
Virtex-6
ML605
Host Datasheet Rev1.4
Reference Design Document Rev1.0
Demo Instruction Document Rev1.2
Evaluation demo file
Get password page
ZC706 KC705 SP605 ML605
Demo Video - - - -
Device Datasheet Rev1.4
Reference Design Document Rev1.1
Demo Instruction Document Rev1.3
Evaluation demo file
Get password page
ZC706 KC705 SP605 ML605
Demo Video - - -
FAT32
Data
Recorder
(Device)
FAT32 Data Recorder Presentation Rev1.0
Reference Design Document
Demo Instruction Document
Evaluation demo file
Get password page
Demo Video


Free Bit file for evaluation

USB3.0(device)-IP
evaluation on SP605
Video Clip on Youtube
DesignGateway provide 1-hour limited bit file. You can evaluate USB3.0-IP core on Xilinx ML605 or SP605 board before purchasing the IP core.
For the evaluation with SP605/ML605/KC705/ZC706, USB3.0-FMC adaptor board is necessary.(P/N: AB07-USB3FMC). Please ask Design Gateway.

Go to Registration page to get password


Performance

USB3.0-IP core can achieve maximum performance of current USB3.0 system.
USB3.0-IP core evaluation on SP605
(with AB07-USB3FMC adaptor board)
USB3.0-IP core Host Reference Design
Support FAT32 commands

Application: FAT32 data recording system (Device Side)

You can easily build FAT32 data recorder system with USB3.0 Device IP core.

System Overview



Features

  • PC recognizes as FAT32 external storage without any driver for Windows or Linux!
  • FAT32 data recorder reference design is available.
  • Free evaluation bit file for Xilinx FPGA boards.

Inquiry/Purchase

Part Number Supported Devices

Host IP

USB3H-IP-SP6 (USB3H-IP002) Spartan-6
USB3H-IP-VT6 (USB3H-IP003) Virtex-6
USB3H-IP-KT7 Kintex-7
USB3H-IP-ZQ7 Zynq-7000

Device IP

USB3D-IP-SP6 (USB3D-IP002) Spartan-6
USB3D-IP-VT6 (USB3D-IP003) Virtex-6
USB3D-IP-KT7 Kintex-7
USB3D-IP-ZQ7 Zynq-7000
Accessories for evaluation Description
AB07-USB3FMC USB3.0-FMC adaptor board for Xilinx FPGA Boards
USB3.0 TypeAtoA cable(1m) is attached.
* Support FMC I/O voltage 2.5V only (does not support 1.8V-I/O such as VC709)


Alliance Partner


Design Gateway Co., Ltd.

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