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[ Gigabit IP core Series ] Ultra High-speed Storage & Network Solutions

Design Gateway provides various ultra high-speed interface IP cores .These IP cores provides not only high-performance, high-reliability, small resource usage, simple interface, but also includes rich technical documents, free evaluation, adapter boards and video demo clips. You can quickly determine the suitable IP core for your project in a short time. More information for [Gigabit IP core Series] Watch Performance Demo Video Clip of Gigabit IP cores on Youtube

Ultra High-speed Storage & Network Solutions [ NVMe IP ] Directly connect NVMe SSD without DDR!! NVMe IP core interfaces Ultra high-speed PCIe SSD without CPU and external memory. It is the best solution for applications which require ultra high-speed performance with compact system. NVMe IP for Xilinx NVMe IP for Altera [ AHCI PCIe SSD IP ] Support AHCI PCIe SSD! APS IP core interfaces Ultra high-speed AHCI PCIe SSD without CPU and external memory. It is the best solution for applications which require ultra high-speed performance with compact system. APS IP for Xilinx APS IP for Altera [ SATA IP ] High-performance & High-reliability core certificated by NASA SATA IP core compliant with the Serial ATA specification revision 3.0. This IP core provides link layer. Transport layer and PHY layer are provided as reference design. It can connect with SATA3 HDD/SSDs directly without external PHY chip. This IP is suitable for applications which require high-capacity and ultra high-speed performance. We provide various options such as RAID, hard logic HOST controller and AHCI with Linux. SATA IP for Xilinx SATA IP for Altera [ TOE10G IP ] 10GbE TCP/IP Stack Implementation By All HW Logic without CPU! This IP core is the epochal solution implemented without CPU. Usually TCP processing is complicated and needs expensive high-end CPU. Because TOE10G-IP core automatically takes over all functions of TCP/IP protocol which needs high-speed operation by hardware logic only. It also supports Full Duplex transmission and Multi-session. TOE10G IP for Xilinx TOE10G IP for Altera [ TOE1G IP ] 1GbE TCP/IP Stack Implementation By All HW Logic without CPU! This IP core is the epochal solution implemented by hardware logic only without CPU. It also supports Full Duplex transmission. We can provide real application reference designs such as FTP server demo and 2 port demo design. TOE1G IP for Xilinx TOE1G IP for Altera [ UDP IP ] UDP/IP Stack Implementation By All Hardware Logic without CPU! UDP IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for Xilinx FPGA. It helps you to reduce development time. UDP IP for Xilinx [ USB3.0 IP ] Easy to apply to FAT32 Data Recorder System!! USB3.0-IP core complaints with the USB 3.0 specification Revision1.0. This IP core provides link layer and protocol layer. Physical layer interfaces to PHY chip by TI. Mass storage class reference design is included in the IP core license. You can start your development from the design bit by bit. USB3.0 IP for Xilinx USB3.0 IP for Altera [ SDXC IP ] Support ExFAT/FAT32 filesystem SDXC IP core compliant with SD Specifications Version 3.01 and support both High-speed SD card (Class 6), SDHC card and SDXC card. It supports SDR50 mode and achieves High-speed transmission up to 50MB/s. More Information News [ NVMe IP ] BRAM version Released!! NVMe-IP is epochally improved to support BRAM operation without external memory such as DDR. More Information for Xilinx More Information for Altera Technical Updates NVMe-IP Xilinx NVMe IP Datasheet Rev1.5 - Updated NVMe IP Reference Design Document Rev1.2 - Updated NVMe IP Demo Instruction Document Rev1.6 - Updated NVNe IP Presentation Rev1.5 - Updated Altera NVMe IP Datasheet Rev1.1 - Updated NVMe IP Reference Design Document Rev1.1 - Updated NVMe IP Demo Instruction Document Rev1.2 - Updated NVNe IP Presentation Rev1.2 - Updated Event PACIFIC TELECOMMUNICATIONS COUNCIL (PTC'17) Date : 15 - 18 January 2017 Place : Hilton Hawaiian Village Waikiki Beach Resort, Honolulu, Hawaii More Information DesignCon 2017 Date : 31 January - 2 February 2017 Place : Santa Clara Convention Center, Santa Clara, CA USA More Information Broadcast Engineering Society India (BES EXPO 2017) Date : 2 - 4 February 2017 Place : The Leela Ambience Convention Hotel, New Delhi, India More Information Privacy Protection Policy DesignGateway recognizes the importance of personal information protection, and strive to protect personal information. We absolutely do not transfer it to a third party. Distributed stop / Address change / Register If you do not wish us to send or if your E-mail address is changed, please contact following page. https://dgway.com/mailmaga.html 発行者 DesignGateway Co., Ltd. https://dgway.com/ Mail：ip-sales@design-gateway.com | About Us| Contact| (c) 2016 Design Gateway Co., Ltd.